Studying in The University of Auckland (PhD) |
- |
Li, Jiale (enrolled in August, 2023) (CSC scholarship holder)
|
- |
Liu, Zhihang (enrolled in June, 2023) (CSC scholarship holder)
|
- |
Yue, ZongCheng (enrolled in August, 2022) (CSC scholarship holder)
|
- |
Marami, Javad (Part-time) (enrolled in February, 2021)
|
- |
Lo, Chunyan John (enrolled in July, 2019)
|
- |
Zhong, Brian (Part-time) (enrolled in February, 2019)
|
|
|
Graduated in The University of Auckland (PhD, Main supervisor) |
- |
Ma, Longyu Sean (2023) (Investigation of Optimization for QC-LDPC Code Decoders on Reconfigurable Hardware Platforms and Potential Applications)
|
- |
Valencia, Raul (2021) (Neuroevolved Binary Neural Networks)
|
|
|
Graduated in The Hong Kong
Polytechnic University (PhD, Co-supervisor) |
- |
Zhang, Pangwei (2021) (Protograph-based Low-density Parity-check Hadamard Codes)
|
- |
Jiang, Sheng (2021) (Digital Design and Optimization of Ultimate-Shannon-Limit-Approaching Channel Codes)
|
|
|
Graduated in The Hong Kong
Polytechnic University in 2014 (Eng.D.) |
- |
Ng, Chi-wai (Analysis
and development of short-distance wired communications) |
|
|
Graduated in The Hong Kong
Polytechnic University in 2014 (MSc with
dissertation) |
- |
Lu, Qing (Architecture
design of QC-LDPC decoder with cyclicly-coupled codes) |
- |
Chen, Cheng (Implementation
of TCP/IP protocol based on FPGA) |
|
|
Graduated in The Hong Kong
Polytechnic University in 2013 (MSc with
dissertation) |
- |
Fan, Jianfeng (Implementation of Cyclic-Layered QC-LDPC decoder on FPGA) |
|
|
Graduated in The Hong Kong
Polytechnic University in 2014 (MPhil) |
- |
Zhou, Hongxia (Routability-driven
floorplanning of analog and mixed-signal circuits) |
|
|
Graduated in The Hong Kong
Polytechnic University in 2010 (MPhil) |
- |
Lu, Jingwei (Fundamental
research on electronic design automation in VLSI design: routability) |