Readings

• Hennessy & Patterson, Computer Architecture: A Quantitative Approach (3rd Ed.), 2003, Morgan Kaufmann, San Francisco, CA, USA.
  • Chapter 1
  • Chapter 2.1-11
  • Chapter 3.1-4, 3.6-7
  • Chapter 5.1-2
  • Chapter 6.1, 6.3, 6.5, 6.7-8
• James E. Smith, "Characterizing computer performance with a single number," Communications of the ACM, Vol. 31, #10 (October 1988), pp 1202-1206.
• LaMarca and R.E. Ladner, "The Influence of Caches on the Performance of Sorting," Proceedings of the Eighth Annual ACM-SIAM Symposium on Discrete Algorithms, January, 1997, pp. 370-379.
• W.A. Wulf, Compilers and computer architecture, IEEE Computer, 14(8), pp. 41-47, 1981.
• R. M. Tomasulo, "An efficient algorithm for exploiting multiple arithmetic units," IBM Journal of Research and Development, Vol. 11, January 1967, pp. 25-33.
• N.P. Jouppi, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, ISCA-17, pp. 364-373, May 1990.
• W.-H. Wang, J.-L Baer, & H.M. Levy, "Organization and performance of a two-level virtual-real cache hierarchy," ISCA-16, pp. 140-148, June 1989.
• P. Sweazey and A.J. Smith, A class of compatible cache consistency protocols and their support by the IEEE Futurebus, Proc. Thirteenth International Symposium on Computer Architecture (ISCA-13), Tokyo, Japan, pp. 414-423, June 1986.
• L. Lamport, How to make a multiprocessor computer that correctly executes multiprocess programs, IEEE Transactions on Computers 28(9), pp. 690-691, 1979.
• R. Rajwar & J.R. Goodman, Transactional execution: toward reliable, high-performance multithreading, IEEE Micro, 23(6), pp. 117-125, November/December 2003.
• L.M. Censier & P. Feautrier, A new solution to coherence problems in multicache systems, IEEE Transactions on Computers 27(12), pp. 1112-1118, Dec. 1978.
• J. Crawford, Architecture of the Intel 80386, Proc. International Conference on Computer Design (ICCD) pp. 155-160, October 1986.