Resources: COMPSCI 703 Semester 1, City Campus

This is a list of required reading for CS703 for 2010.

An extended (and disorganized) list of papers of significance and relevance to computer architecture can be found here.

• Olukotun & Hammond, The Future of Microprocessors IEEE Queue, September 2005.
• Hennessy & Patterson, Computer Architecture: A Quantitative Approach (4th Ed.), 2007, Morgan Kaufmann, San Francisco, CA, USA.
  • Chapter 2 (18MB file!)
• P. Sweazey and A.J. Smith, A class of compatible cache consistency protocols and their support by the IEEE Futurebus, Proc. Thirteenth International Symposium on Computer Architecture (ISCA-13), Tokyo, Japan, pp. 414-423, June 1986.
• James E. Smith, Characterizing computer performance with a single number, Communications of the ACM, Vol. 31, #10 (October 1988), pp 1202-1206.
• Mark Hill, Processors should support simple memory-consistency models, IEEE Computer, 31(8), pp. 28-34, August 1998.
• How to Survive the Multicore Software Revolution (or at Least Survive the Hype) (pdf)
• M. Herlihy and J.E.B. Moss, Transactional Memory: Architectural Support for Lock-Free Data Structures, Proc. International Symposium on Computer Architecture (ISCA-93), ACM Press, 1993, pp. 289-300. (required reading for Final Exam, not Test)
• J.R. Larus, R. Rajwar, Transactional Memory, (available for free download as a pdf on UoA campus) Morgan and Claypool Publishers, 2006. (Chapters 1 & 2 are required reading for Final Exam, not Test)
• R. Rajwar & J.R. Goodman, Speculative Lock Elision: enabling highly concurrent multithreaded execution, 34th Annual International Symposium on Microarchitecture (MICRO-34), December 2001, pp. 294-305.

This is a list of recommended reading for CS703 for 2010. In most cases, it is also the source for accessing the readings.

• Wikipedia: "Cache Memory"
  http://en.wikipedia.org/wiki/CPU_cache
• M. Hill & A.J. Smith, Evaluating Associativity in Caches, IEEE Computer, 29(12), pp. 66-76, Dec 1996.
• Jon Stokes, Understanding CPU caching and performance, http://arstechnica.com/old/content/2002/07/caching.ars
• R. Rajwar & J.R. Goodman, Transactional execution: toward reliable, high-performance multithreading, IEEE Micro, 23(6), pp. 117-125, November/December 2003.
• D Dice, Y Lev, M Moir, D Nussbaum, “Early experience with a commercial hardware transactional memory implementation,” ASPLOS09, pp. 157-168, (March 2009).
• M Herlihy, V Luchangco, M Moir, W Scherer III, "Software transactional memory for dynamic-sized data structures (DSTM)," Twenty-Second ACM Symposium on Principles of Distributed Computing (PODC), 2003, pp. 92-101.
• M.J. Flynn, Very high-speed computing systems, IEEE Proceedings, 54(12), pp. 1901-1909, 1966.
• R.M. Russell, The CRAY-I computer system, CACM, 21(1), pp. 63-72, 1978.
• AMD Advanced Synchronization Facility: Proposed Architectural Specfication, Advanced Micro Devices, Publication #45432(revision 2.1), March 2009.